1. Field of the Invention
The present invention relates to a coating and developing apparatus of which a processing unit processes a substrate such as a semiconductor wafer or a liquid crystal display glass substrate (an LCD substrates), one transferring means transfers the substrate to another transferring means through a processing unit, and the other transferring means transfers the substrate to a plurality of downstream processing units. For example, the present invention relates to a coating and developing apparatus that forms a resist film on a substrate and performs a developing process for the exposed substrate, in particular to a transferring technology of an interface portion that is disposed between the apparatus and an aligner and that transfers an exposed substrate to a region in which a developing process is performed.
2. Description of the Related Art
In a manufacturing process for semiconductor devices and LCD substrates, a resist coating process is preformed for substrates using a technology called the photolithography. In this technology, a resist solution is coated on for example a semiconductor wafer (hereinafter referred to as a wafer) as a liquid film. With a photo mask, the resist film is exposed. Thereafter, a developing process is performed for the resultant substrate. As a result, a desired pattern is formed on the substrate. The photolithography technology is accomplished by a series of these processes.
A system that integrates a coating and developing apparatus that performs those processes and an aligner has been known. FIG. 14 is a schematic plan view showing such an integrated system. FIG. 15 is a schematic side view showing a part of the integrated system. FIG. 16 is a schematic diagram describing a transportation path of wafers W in the integrated system. A coating and developing apparatus 1 is composed of a carrier mounting portion 1A on which many carriers C are placed, a processing block 1B disposed on the far side of the carrier mounting portion 1A, and an interface portion 1C. An aligner 1D is connected to the coating and developing apparatus 1 through the interface portion 1C. Disposed in the carrier mounting portion 1A is a transferring arm 11 that transfers wafers W contained in carriers C to the processing block 1B. Disposed in the processing block 1B are a main transferring arm 12 and rack units 13 (13a, 13b, and 13c). The main transferring arm 12 has for example three arms that are capable of advancing and retreating, raising and lowering, and rotating in the horizontal direction. The rack units 13 are disposed on the near side, the left side, and the far side of the main transferring arm 12 viewed from the carrier mounting portion 1A. The rack units 13 have heating units and cooling units that are multiply tiered. The cooling units are accurately temperature controlling units. Disposed on the right side of the main transferring arm 12 viewed from the carrier mounting portion 1A is a liquid processing unit 14. The liquid processing unit 14 has a coating unit (COT) and a developing unit (DEV).
Disposed in for example the rack units 13a to 13c are transferring units (TRS1 to TRS3), a hydrophobic processing unit (ADH), a bake unit, and so forth. The transferring units (TRS1 to TRS3) transfer wafers W between the carrier mounting portion 1A and the processing block 1B, among the rack units 13a to 13c, and between the processing block 1B and the interface portion 1C. The baking unit performs a heating process for wafers W that have been exposed.
Disposed in the interface portion 1C are for example an accurate temperature controlling unit (CPL), a periphery aligner (WEE), and a buffer cassette (SBU). A transferring arm 15 that transfers wafers W among these modules and between each of these modules and the processing block 1B is disposed. The transferring arm 15 is capable of advancing and retreating, raising and lowering, and rotating in the horizontal direction. In addition, the transferring arm 15 is capable of accessing a loading stage 16 and an unloading stage 17 disposed in for example the interface unit 1C. Thus, the transferring arm 15 is capable of transferring wafers W between the interface portion 1C and the aligner 1D.
In the foregoing system, a wafer W contained in a carrier C placed on the carrier mounting portion 1A is loaded into the processing block 1B through the transferring arm 11. The coating unit (COT) coats a resist solution on the wafer W. Thereafter, the wafer W is transferred to the interface portion 1C and the aligner 1D in these orders. The aligner 1D exposes the wafer W. After the wafer W has been exposed, the wafer W is transferred to the developing unit (DEV) of the processing block 1B in the reverse path. The developing unit (DEV) develops the wafer W. Thereafter, the wafer W is returned to the carrier mounting portion 1A through the transferring arm 11. Before and after the coating and developing processes are performed for the wafer W, a pre-process and a post-process such as a heating process and a cooling process are performed in the rack units 13 (13a, 13b, and 13c) for the wafer W.
To perform the foregoing processes for a wafer W, a path is pre-programmed. Next, with reference to FIG. 16, an example of the path will be described. In FIG. 16, PAB represents a pre-baking unit, PEB represents a post-exposure baking unit, and POST represents a post-baking unit (post-development baking unit). As shown in FIG. 16, a wafer W is transferred from a carrier C to the processing block 1B by the transferring arm 11. Thereafter, the main transferring arm 12 transfers the wafer W to the TRS1, the ADH, the COT, the PAB, and the TRS2 in their order. Thereafter, the transferring arm 15 transfers the wafer W to the TRS2, the CPL3, the WEE, the SBU, and the loading stage 16 in their order. After the wafer W is processed in the ADH, in reality, a temperature controlling process is preformed for the wafer W. However, due to the limited space of the drawing, the temperature controlling process is omitted. After the aligner 1D performs an exposing process for the wafer W, it is transferred to the unloading stage 17 and the TRS3 in their order by the transferring arm 15. Thereafter, the wafer W is transferred to the TRS3, the PEB, the CPL, the DEV, the POST, and the CPL in their order by the main transferring arm 12 and then returned to the carrier C by the transferring arm 11.
A transportation schedule that describes timings all wafers of the lot are transferred to modules is stored in a memory. When the transferring arm 11 and the main transferring arm 12 are referred to as the transferring system, it transfers wafers W to the TRS1, the ADH, the COT, the PAB, the TRS2, the TRS3, the PEB, the CPL, the DEV, the POST, and the CPL in their order as denoted by dotted lines shown in FIG. 16. A coating and developing apparatus that takes out a wafer W from a carrier (cassette) and successively transfers it to processing units is disclosed in Japanese Patent Laid-Open Publication No. 2001-351848 (paragraph 0003 and paragraphs 0093 to 0099) issued by Japan Patent Office.
When lots are changed, if it takes a long time to replace reticles and change parameters or an alarm takes place in the aligner 1D, a wafer may not be unloaded from the aligner 1D for a time being. Thus, after reticles are changed, wafers may be unloaded from the aligner 1D. However, since the main transferring arm 12 transfers wafers W in accordance with the schedule, after the main transferring arm 12 receives one exposed wafer from the TRS3 and transfers the wafer to the PEB, the main transferring arm 12 cannot be returned. Thus, although the wafer has been exposed, it is left on the unloading stage of the aligner 1D until the main transferring arm 12 transfers the wafer to the PEB in the next cycle.
Thus, the time after the wafer is exposed until it is heated (pre-heat elapse time) becomes longer than the pre-heat elapse time for each of other wafers. To obtain desired pattern line widths, parameters such as exposure time, exposure amount, heating temperature and heating time in the PEB, and so forth are predetermined. At this point, the pre-heat elapse time is also predetermined. When a chemically amplifying resist is used for fine patterns, it is thought that after the resist is exposed, the pre-heat elapse time adversely affects the result of the developing process. Thus, if the pre-heat elapse times for wafers vary, as pattern line widths are miniaturized, their uniformity lowers. As a result, the yield of the final products may deteriorate.
When an exposed wafer is left stagnant in the interface portion 1C, the aligner 1D becomes incapable of exposing the wafer. Thus, the throughput of the aligner cannot be fulfilled. To prevent this problem, a buffer may be disposed in the interface portion 1C. However, in this case, the number of transferring processes becomes large. As a result, the throughput of the entire system cannot be fulfilled.